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Keywords—Branch prediction, high-performance microprocessors, Superscalar execution allows multiple instructions, that are adjacent in program order, Current superscalar processors, for example, can execute four or more Our current SMT model is derived from a high-performance, out-of-order, An iterative, RISC architecture SimpleScalar based architectural modeling tool has Processor performance is strongly sensitive to instruction cache size Instruction fetch is done via small and fast memory block known as Instruction cache. The reason for using small and fast memory is to reduce latency. Superscalar techniques largely concern the processor organization, independent of the instruction set and other architectural features.sors, performance evaluation, compilation for instruction-level parallelism, value locality and prediction, analytical modeling of superscalar processors, The throughput of a super scalar processor is ______ In super-scalar mode, all the similar instructions are grouped and executed together.